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Do you need an image processing algorithm developed or a software defined radio or even a combination of the two?

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jefflaw
 
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Joined: Fri Aug 22, 2014 2:14 pm
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Jeffery R. Lawrence
   Fri Aug 22, 2014 2:26 pm

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Jeffery R. Lawrence

Permanent Linkby jefflaw on Fri Aug 22, 2014 2:26 pm

Objective
Empower great ideas utilizing social collaboration to bring solutions that solve world problems efficiently through the facilitation of creator owned licensing and allowing those individuals to balance work with life.

Experience
April 2014 - Present Peak Imaginations, Inc. Mt. Hood Parkdale, OR
President and CEO/Chairperson
• Developing Business Plan, Creating Cash-flow spreadsheets, Incorporating. Wearing various hats including the architecture and design, schematic, pcb layout of a wireless device...More to come. Web design php coding. Reorganizing how life interacts with work and releasing concepts of empowerment through facilitating others to embrace their potential. Check out my website.
• Consulting on the analytic chemistry involved in drug screening using the highly integrated instrumentation High Pressure Liquid Chromatography (HPLC) - Mass Spectrometer (MS) absciex triple quad 5500...This instrument is awesome.

July 2012 - March 2014 UTC Aerospace Systems
Cloud Cap Technology Hood River, OR
Staff Electrical Engineer
• Architected and Implemented H264 video processing on a Xilinx spartan6 FPGA for the capture and display of GigE Vision Camera for the TASE400 DXR and LRS products. VHDL for the macroblock reordering of luma and chroma for the H264 IP. Created automated Verilog test bench with file I/O reads with VHDL modules. Integrated Xilinx Video Processing IP for chroma resampling and VDMA. AXI-Stream interconnects to support future product processing expansion.
• Reviewed ISR - Gyro, Accelerometer, Pressure sensor results from numerous temperature test runs to determine optimum calibration effectiveness
• Schematic and pcb layout lead of an FPGA design to take GigE vision video data and buffer it for a TI DSP as part of the first Digital Video solution for this design center (all prior video was analog and low resolution). DDR3, SGMII, HD-SDI
• Worked through numerous issues integrating new Intellectual Property purchased from outside sources as well as integrating FPGA solutions into a companies products that had never used FPGA's
• Trained engineers to review and understand fundamentals of circuit components such as derating of ceramic capacitors and integrated design reviews onto the fundamental processes of the engineering designs. Thus, product quality has improved greatly.

Nov 2010 - June 2012 Meteorcomm, LLC Renton, Wa
RF Project Engineer
• Responsible for electrical product design, test and documentation tasks associated with the development of a 30W wireless transceiver product at Meteorcomm to support a railroad communication system for Positive Train Control (PTC). Designed digital main board including DDR, Coldfire, Altera FPGA and CPLD, spansion flash memory and TI DSP translating digital to RF with a Quadrature Digital Upconverter,

April 2010 - Nov. 2010 TEK Systems Kent, Wa
RF Project Engineer
• Responsible for electrical product design, test and documentation tasks associated with the development of wireless transceiver product at Meteorcomm to support a railroad communication system.
• Provide guidance on GPS designs and testing as well as low power circuit optimizations of the master board design for a software defined radio (SDR)
• Coordinate technicians and technical staff activities related to the transciever product

March 2007 – Jan 2010 SAIC (http://www.saic.com/) Kent, Wa
Science Applications International Corporation
Space and Geospatial Intelligence Business Unit
Hardware/FPGA/RTL Engineer
• Verilog coding of parallel to serial media access control modules and integrating into a prototype development platform with access to a TI 6713 DSP. Multiple clock domain synchronization. Test bench creation.
• Five Circuit Designs: (1) Power module design for VME rear transition modules (plus circuit board layout). Supplies current to 50Amp low voltages.
(2) GPS clock receiver board (plus circuit board layout) SPICE analysis.
(3) Designed a 6U board that included a XC4VFX100 Xilinx FPGA and an Analog Devices Quadrature Digital Upconverter AD9957. This has a high performance immunity to digital noise in the analog mixed-signal section.
(4,5) (SDR) Large Breadboard and production 2”x2.5” Ultra Low Power Battery Operated long life-time device, Blackfin DSP, Wireless RF with QDUC, GPS receiver
• Documentation of designs, lab notebooks, verification test plans and board test plans. Research key technologies and equipment. Use of pattern generators, oscilloscopes, spectrum analyzers, and power load equipment. Development/training of a Junior Engineer

Nov 2004 – June 2006 BARCO (http://www.barco.com/) Beaverton, OR
Modality Engineering Manager
• Project Definition and Sales Hat: visited clients to translate hardware and software system needs into custom projects. Defined technical presentations and white papers. Highly visible person representing Barco at trade shows such as RSNA in Chicago. 40-50% travel
• Project Manager Hat: Display system project management that includes transmitting video and USB data over two strands of duplex 100 meters fiber optic cable. Managed both electronics and mechanical engineering resources in multiple US states, Belgium and includes managing consultants. Customer was very happy with working systems.
• Design Architect Hat: Architect custom systems to meet features and design goals for customers. Direct experience designing non-ferrous and EMI shielded systems. Worked with suppliers of custom products such as connectors, inductors, backlight inverters, and front glass manufacturers to obtain supplies of essential system components. Defining Statement of Work (SOW) for required consulting.
• Senior Hardware Design Engineer Hat: Veribest schematic capture. FPGA architecture and coding of a novel approach to image processing improving the LCD response time of LCD displays. Barco markets this as Response Time Improvement System (RTIS). Created an RTIS demonstration system to show customers and for use in clinical trials. Includes ModelSim 6.1 simulation and test bench creation.
• Application Engineer Hat: Provided customers with information on LCD displays, calibration, human vision perception, and information on light to provide high quality medical viewing experience to radiologists and clinical personnel. Create calibration spreadsheets in Excel for various display systems and gamma corrections.

May 2001 – Nov 2004 BARCO (http://www.barco.com/) Beaverton, OR
Senior Hardware Engineer
• Project Hardware Lead: FPGA design of the video section to pump data on a two port Five Megapixel analog output Video Card operating at 550MHz Pixel Clock. Cut design time because of good VHDL design for re-use techniques 5MP2FH. Re-architected system blocks to create a re-useable method of pipelining video data at multiple clock frequencies and pixel formats. Design solution included use of DDR IO’s addressing 512MB. Designed for a Xilinx Virtex-II FPGA (XC2V3000) using VHDL. Product Name: BarcoMed 5MP1HM
• Project Hardware Lead: Designed/Documented two 170 MHz system blocks (Screen Refresh and Look Up Table Blocks) in a Xilinx Virtex-II FPGA (XC2V3000) using VHDL for a 5 MegaPixel Flat Panel Video Card. Redesigned/Documented five system blocks (PCI Access Register Block, Video Timing, Video Signature, Temporal Dither, and Hardware Cursor Blocks). These Designs required synchronization between three clock domains. Product Name: BarcoMed 5MP2FH
• ALDEC and ModelSim Simulation both Behavioral and RTL. Synopsis/XST Synthesis. Created testbench models.
• Designed a parallel boot loader/FLASH EPROM programmer for the Xilinx-II in a XC95144 CPLD and PCBoard design schematic entry using Mentor Veribest.
• Drafted three novel approaches to delivering video. 1) Flexible Video Initiative for video delivery exceeding 20Gb/s 2) Screen Refresh with Rotation 3) Network Video Server
• Drafted an FPGA Design Procedure and an FPGA Functional Specification Procedure

July 1997- March 2001 PMC-Sierra (www.pmc-sierra.com) Beaverton, OR
Systems Validation Design Engineer
• Designed/Specified a Link Layer interface FPGA operating at 104MHz interface that concatenated two PL3 buses 2.5Gb/s to one 3.5Gb/s using XILINX 2000e
• Documented test plans for ASIC validation conformance to Ethernet standards. Debugged internal chip system blocks design errors by examining the system at a given test state and compared to Verilog code. Tested chip conformance to standards using sampling and digitizing oscilloscopes, Logic Analyzers, pattern generators, protocol analyzers (Smartbits and IXIA).
• Documented engineering designs that described details required for PCB routing. Lead a routing vendor in three high-speed controlled impedance PCB switch designs. Analyzed transmission line characteristics with SPICE for capacitive loading of CACHE memory systems that included 1.5MB SSRAM and 12MB SDRAM.
• Designed/prototyped three Fast Ethernet and Gigabit Switches that used 83MHz SSRAM and SDRAM and a 135MHz SERDES backplane. Reviewed customer high speed Ethernet switch designs. Defined the design for a card cage sixteen port gigabit or 64 port 10/100Base-T Ethernet switch system.
• Leader of a small team that completed circuit board designs, ASIC validation, and firmware groups debug support. Lead Validation Engineer on six ASIC’s in four years.

Aug 1995– June 1997 nCUBE (http://en.wikipedia.org/wiki/NCUBE) Beaverton, OR
• Ask for more detail

Summer 1995 Leppo Instruments Beaverton, OR
• Ask for more detail

April 1994 - June 1995 Supra Corporation (http://en.wikipedia.org/wiki/Supra%2C_Inc.) Albany, OR
• Ask for more detail

1988- March 1994 Oregon State University Corvallis, OR

Education
• B.S., Electrical and Electronics Engineering
• Minor in Chemistry
Fall 1996 Portland State University Portland, OR
• VLSI Design Automation
1997, 2000 QUALIS Beaverton, OR
• Verilog for High Level Design Verification Oct. 1997
• Deep Knowledge in VHDL Synthesis Sept. 2000
2001-2003 XILINX San Jose, CA
• ISE Design Entry Oct. 2001
• Fundamentals of FPGA Design Oct. 2001
• Designing for Performance Oct. 2001
• Advanced FPGA Implementation Jan. 2003
2003-2004 Barco Beaverton, Or
• Path of Dialog Feb. 2003
• Berlitz Dutch I 2004
2003-2004 Insight Beaverton, Or
• Xilinx MGT Workshop RocketIO Dec. 2003
• Virtex-II Pro™ UltraController™ Workshop Apr. 2004
2003-2006 OHSU/OGI Beaverton, Or
• Peer Mentoring Seminar Dec. 2003
• BME568: Analysis and Modeling of Auditory and Visual Processing… Spring 2004
• Project Management Training Sept. 2004
• Essential Presentation Skills Sept. 2004
• Math530: Probability and Statistical Inference for Scientists and Engr Winter 2005
• Program Management - Planning, Scheduling, and Controlling Feb. 2005
• EE588: Introduction to Biomedical Engineering March 2006
2004 Mentor Graphics Beaverton, Or
• ModelSim Training Feb. 2004
2005 FastEdges Beaverton, Or
• Signal Integrity & High Speed Methodology Dec. 2005
2006-2009 Mindshare Beaverton, Or
• PCI Express Jan. 2006
• Comprehensive USB 2.0 Embedded System Architecture Dec 2009

Emphasis
Leader, system architecture and specification documentation, project management, Ethernet 802.3, Fiber optic communication systems, FPGA design, RTL coding, DVI, PCI, USB, High-Speed digital design, schematic entry, video display systems, optic and copper physical layer media, sensor and acquisition systems, computer networking, wireless transmission

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